1. Field of the Invention
This invention relates to a terminating and clamping circuit, and more particularly to a terminating and clamping circuit used in a transmission bus in a computing system.
2. Description of the Related Art
Communication systems, in particular computing systems, and their devices communicate in a binary language of voltage waveform signals (wave) that translate to either a xe2x80x9c1xe2x80x9d or a xe2x80x9c0.xe2x80x9d A wave that represents a xe2x80x9c1xe2x80x9d has a predetermined maximum peak voltage and a predetermined minimum voltage. A wave that represents a xe2x80x9c0xe2x80x9d has a predetermined maximum peak voltage that is considerably lower than a wave representing a xe2x80x9c1xe2x80x9d or the wave may have no value (a flat wave with a zero voltage value) and a predetermined minimum voltage. In complementary metal oxide semi-conductor (CMOS) circuits, the peak of a wave representing a xe2x80x9c1xe2x80x9d is the voltage value VDD (the xe2x80x9chighxe2x80x9d value). A peak of a wave representing a xe2x80x9c0xe2x80x9d is the voltage value VSS (the xe2x80x9clowxe2x80x9d value). Typical applications set the high value at some positive voltage, for example 1.2 volts, and the low value is set to zero volts.
In a communication system a device can be a driver device transmitting the signals; a device can be a receiver device accepting and computing the signal; or the device may act as both a transmitter and a receiver device. A communication system may be a circuit and the transmission bus can be an electrical trace line capable of carrying the signals. The receiver determines what the minimum value of the peak voltage is that represents xe2x80x9c1xe2x80x9d and the maximum value of the peak voltage that represents xe2x80x9c0.xe2x80x9d
As a wave is launched from the driver device it travels along the bus until the receiver device receives the wave. The transmitted incident wave may be totally absorbed, totally reflected, or some combination between absorbed and reflected. After a propagation delay, a wave can be reflected back along the bus. Any reflection of a wave that travels back along the bus leads to noise that affects subsequent transmitted waves. When a driver device sends an initial wave, this wave may be reflected back from the receiver device. A reflected wave adds to the value the incident wave and of subsequent wave(s) sent from the driver device thus exceeding the voltage high reference value VDD. In other instances, reflected waves may cancel out a subsequent transmitted wave or waves.
The described problem with reflected waves is known as inter-symbol interference (ISI) and leads to noise and erroneous transmission along the bus. Reflected waves eventually settle and the noise is eliminated, however, when transmitting waves at a greater rate than settling allows, waiting for settling of reflected waves is not acceptable. In a computing system where the electrical trace line (bus) is about three inches long, a transmitted wave that is reflected may take about 10 to 20 nanoseconds to oscillate and settle. When transmitting signals at the rate of 250 Mhz, there is insufficient time to wait for a reflected wave to settle. Therefore in many devices the incident wave is made to be large enough so that the receiver senses the value transmitted without the need of the reflection to settle down. This method of transmission is called incident switching.
In typical applications, a trace line or bus connects one device to another device. In these point to point transmissions, reflected waves and noise can be addressed by clamping and terminating circuits that clamp a transmitted wave to the set high and low wave parameters and terminate a received wave.
A driver launches a large enough wave to ensure incident switching to offset subsequent reflection and noise problems. The transmitted wave is reflected at the receiver per the following equation:
VR=VIxc3x97[Ztermxe2x88x92Ztrans]/[Zterm+Ztrans]
VR represents a reflected wave. VI represents an incident wave or received wave. Zterm is the impedance of the termination device or circuit. Ztran is impedance along the transmission bus. If there is no termination, the impedance value at the termination end being zero, the reflected wave is equal to the incident wave (absolute value) and there is complete reflection. A completely reflected wave therefore requires a large enough wave to be launched (transmitted) that would offset the reflected wave. In addition the wave must be large enough to convey the peak voltage value. Therefore the actual transmitted wave is set to a large enough value. This, however, causes unneeded overshoots and undershoots at the receiver.
An additional physical limitation is encountered in transmitting waves as described in the proceeding. In transmitting a wave, the voltage waveform VT, follows the equation:
VT=VDDxc3x97[Ztran/(Zdriver+Ztran)]
where VDD is the voltage reference high value, Zdriver is the impedance at the driver device, and Ztran is the impedance along the transmission line. To vary the size or voltage value of the transmitted waveform, the impedance values of the transmission line or the driver device must be changed, however, the value of the transmitted waveform can never be greater than VDD.
Addressing ISI and noise problems become a greater problem in a communication system with three devices. Now referring to FIG. 1, illustrated is a system where three devices are connected: a CPU 10, a data buffer 20, and a memory 15. CPU 10 is a driver and receiver device. Likewise, data buffer 20 and memory 15 also are devices capable of driving and receiving signals (waves). When one device drives a signal, the other two devices act as receivers of that signal. CPU 10 is connected to the data buffer 20 by a main bus 25. A split or spur bus 14 from main bus 25 connects memory 15 to the CPU 10 and data buffer 20.
The system illustrated in FIG. 1 can reside as a module in a computer server system. A number of modules can be contained in the computer server system. As illustrated in FIG. 1 each module consists of a central processing unit (CPU) 10, a data buffer 20, and memory 15, the memory 15 being a static random access memory device (SRAM). Each of the three devices acts as a driver or a receiver, being able to send or receive signals along the transmission busses or trace lines that connect the three devices. In one application the SRAM or memory 15 is linked to the main bus 25 by a relatively short spur bus 14. The spur bus 14 can be {fraction (1/10)}th the length of the main bus 25. Transmission speeds along the main bus 25 and the spur bus 14 approach about 250 Mhz. It has been found that along the transmission bus, overshoots and undershoots at the data buffer are seen. An overshoot being a signal exceeding the voltage tolerance of the reference high VDD or exceeding the voltage tolerance of the reference low signal VSS. An undershoot is a voltage signal falling below the tolerance values set by VDD or VSS. Overshoots and undershoots may be compensated for by CPU 10 adjusting for the voltage signals as seen by the data buffer 20. Since a third device, the memory 15, also receives the signal along a much shorter transmission line, any adjustments made to compensate for the data buffer 20 adversely affects signals received at the memory 15.
Along the transmission busses waves (signals) can be reflected or absorbed. These signals may be under or over terminated. An under-terminated signal is a reflected signal. An over-terminated signal is a signal that has been compensated to the point that the it has been degraded. Under-terminated or non-terminated bus lines require a larger power output from the driver unit. Since the voltage signal remains the same, current must increase, which leads to an increased rate of current consumption in the driver unit. Proper signal termination is required to prevent reflections and noise along the busses.
In transmitting a waveform along a transmission bus, there is some propagation delay. The propagation delay depends on the length of the transmission line. A wave on integrated circuit trace line, the trace line being the bus, typically takes 180 picoseconds to travel an inch. For a three inch trace line, it takes about 540 picoseconds to a transmitted wave to go from a driver device to a receiver device. Along the spur bus 14 that is {fraction (1/10)}th the length of the main bus 25, the transmitted wave takes a much shorter time to travel.
Signal propagation delay adds to the ISI and noise problem. A driver device, such as the CPU may act as a termination device and terminate the reflected wave. When a split bus is used it becomes even more necessary to clamp and terminate waves. Along with ISI, transmission problems arise with wave propagation delay, transmission timing, and other problems associated with transmitting waves. A signal cannot be clamped and terminated until it is actually received. A dynamic or active termination and clamping circuit therefore is needed at a receiving device to prevent reflections and noise along a bus.
In order to limit overshoots and undershoots of voltages transmitted as signals, clamping circuit devices have been created. These clamping devices typically have one stage that clamps the upper reference voltage signal, and a lower stage that clamps the lower reference voltage signal.
Now referring to FIG. 2, illustrated is a diode clamping circuit. A transmission bus 12 connects a driver device 30 to a receiver device 35. Along the transmission bus 12 an input/output pad 50 connects diode 31 and diode 33. Diode 31 prevents swings greater than VDD, and diode 33 prevents voltage swings greater below VSS. In other words, diode 31 conducts when the voltage swings greater than VDD and diode 33 conducts when the voltage swings below VDD. Diode clamps have the advantage that they are able to clamp only when a signal is received, acting as xe2x80x9cactivexe2x80x9d clamps. Constant clamping circuits on the other hand continuously clamp and can act against transmitted signals forcing a driver device to output unneeded voltage. Diode clamps, however, have their disadvantages. One disadvantage is that a diode to be activated requires reaching a threshold voltage for the diode. This threshold voltage must be reached prior to the diode being able to terminate the voltage signals. In transmitting signals at the rate of 250 MHz, the wait to reach threshold voltage is insufficient for transmission. Diodes are inadequate because they have a bias voltage that must be met along with the sinking voltage that for example may add up to about 1.1 volts before they are effective. In transmitting waveform signals that have 1.2 voltages, diode clamps are ineffective in clamping to high and low signals. Considering the need to reach a threshold voltage, a diode clamp is not fast enough to address the clamping concerns of a high speed transmission bus that may transmit signals at the rate of 250 Mhz. A voltage source may be added that continuously supplies a threshold voltage, however, this presents additional costs and design consideration for a quality voltage source just to provide the threshold voltage to the diode.
Now referring to FIG. 3, a resistor clamping circuit is illustrated. A resistor 36 clamps for over-voltage situations, while resistor 38 clamps for under-voltage situations. Resistors 36 and 38 are connected along transmission bus 12 by input/output pad 50. Unlike a diode clamp that only activates upon when a signal is received, the resistor clamp continuously clips the waves (clips the transmitted voltage). The resistor clamp effectively is fighting the driver device 30 and lowering the voltage, therefore the driver device 30 to properly transmit a signal to the receiver device 35, a large enough signal must be transmitted. Adding a third device 37 connected by a spur bus 14 complicates the situation. As the receiver device 35 receives signals from the driver device 30, the clamping circuit clips and the driver device 30 adjusts its transmission to assure proper transmission to the receiver device 35. The by-product of the voltage adjustment is an improper transmission to the third device 37.
Now referring to FIG. 4, illustrated is a CMOS clamping circuit. A driver device 30 transmits signals to receiver device 35 along transmission bus 12. CMOS device 40, which in this embodiment is a PMOS type device, clips the signal voltage if it exceeds VDD. CMOS device 45, which in this embodiment is an NMOS type device, clips the voltage signal if it drops below VSS. CMOS devices can provide the necessary active clamping needed in a high transmission computer systems. CMOS clamping circuits, however, can act as resistor clamping circuits, if they are not properly biased. Like resistor clamping circuits, CMOS devices, however, can act like resistor clamps and continuously clamp and clip a signal. The clamping continuously occurs even when a received waveform is within the tolerable values, unnecessarily clipping the received waveform.
Now referring to FIG. 5, illustrated is a CMOS clamping circuit with a biasing circuit. This CMOS clamping has an upper stage CMOS device 40 that clips the signal voltage if it exceeds VDD. CMOS device 45 clips the voltage signal if it drops below VSS. Both CMOS device 40 and CMOS device 45 are connected to a transmission bus at input/output pad 50. The gate of CMOS device 40 is connected to the gate of CMOS device 47 which in turn connects to the source of CMOS device 47. The gate of CMOS device 45 is connected to the gate of CMOS device 49 which in turn connects to the drain of CMOS device 49. This particular CMOS clamping circuit uses the CMOS device 47 and CMOS device 49 in the described configuration in order to attain voltage biasing, voltage biasing is needed in order to have an active clamping circuit.
In a CMOS clamping circuit, bias voltage for the CMOS upper and lower stages must be constant for active clamping to take place. If the bias voltages are not steady, there is no clamping of the bus or the clamping is ineffective. The bias voltage at node 64 is VDDxe2x88x92VTP. The bias voltage at node 62 is VTN.
In the CMOS clamping circuit of FIG. 5, a feedback setup to maintain constant current in the biasing circuits is necessary. The current value at node 60 must be maintained in order for the biasing to properly function. A feedback setup must be incorporated to adjust impedance to maintain the constant current at node 60. It is found that a voltage drop occurs, the voltage drop being VDDxe2x88x92VTPxe2x88x92VTN across CMOS device 47 to CMOS device 49. To maintain the constant current at node 60, impedance must be adjusted. Further, although this CMOS clamp provides DC termination, it is ineffective for AC termination.
A need has been felt for a dynamic termination and clamping circuit which reduces noise by actively detecting when overshoots and undershoots occur at the receiver and on detection of an overshoot/undershoot clamps the bus at the rail voltages (reference voltages VSS and VDD), thus providing dynamic termination to the bus. A need is felt for a circuit to allow improved signal integrity at the receiver without sacrificing the speed of the network and noise-margins at the receiver. Further a properly biased active clamping and terminating circuit must be able to operate at all process voltage and temperature (PVT) corners or conditions.
In a communication system that connects transmitters and receivers along a transmission or communication bus, there are reflections leading to overshoots and undershoots which in turn lead to ISI noise; a dynamic clamping and termination circuit provides clamping of the voltage and under voltage waves and also terminates the signal in order to reduce ISI noise.
In one embodiment of the invention a MOS based clamping and termination circuit is used. One MOS transistor clamps to a set over voltage value and another MOS transistor clamps to a set under voltage value. Bias voltages are provided in order for the MOS devices to actively or dynamically clamp when a signal is received.
In a specific embodiment of the invention MOS stage circuits are used a leaker devices to regulate biasing. In the same embodiment, MOS devices are connected to act as capacitors to allow stabilization of the bias voltages.
Another embodiment includes a method for clamping and biasing the clamping stages in order to actively clamp and terminate signals along the communication bus.
One embodiment makes use of a feedback system incorporating operational amplifiers which provide biasing voltages to MOS devices which provide clamping for the under voltage and over voltage signals.